Cadence debuts its next-gen Palladium Z2 and Protium X2 Systems

American computational software company, Cadence Design Systems, Inc. has unveiled its latest Cadence® Protium™ X2 Enterprise Prototyping and Palladium® Z2 Enterprise Emulation systems to simplify increasing system design complexity and time-to-market pressure on businesses.

Based on the firm’s current Protium X1 prototyping and Palladium Z1 emulation platforms, the latest systems offers the most throughput and pre-silicon software validation and pre-silicon hardware debug multi-billion-gate system-on-chip (SoC) designs.

Commenting on the launch, Narendra Konda, Senior Director, Hardware Engineering, NVIDIA Corp., explained that their firm’s high-end graphics and hyperscale designs have become more complex with each generation, with time-to-market schedules continue to become tighten over time.

By utilizing Cadence Palladium Z2 and Protium X2 system’s common front-end flow, NVIDIA is optimizing workload distribution between validation, verification, and pre-silicon software bring-up. With features like 50% higher throughput, faster modular compiler turnaround, and twice the useable capacity, the company can validate its most sophisticated SoC and GPU designs comprehensively and on schedule, added Mr. Konda.

Paul Cunningham, Senior VP & General Manager, System & Verification Group, Cadence, said that pre-silicon verification of latest SoC design necessitates the requirement for a solution with multi-billion-gate capacity that endows both rapid predictable debug and highest performance. Cadence Palladium Z2 emulation is optimized for prompt predictable hardware debug while Protium X2 prototyping is designed for offering best performance multi-billion-gate software validation.

As per Hanneke Krekels, Sr. Director, Core Vertical Markets, Xilinx, Inc., their firm has worked closely with Cadence to ensure Cadence software front-end works effortlessly with Xilinx Vivado Design Suite back-end, enabling ideal capacity and performance benefits.

The closely integrated Xilinx and Cadence front-to-back flow enables software developers to utilize the platform as early as possible during the development flow and to emphasize on software development and design validation rather than prototype bring-up.

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